Multiple channel selection circuits are used in a wide variety of applications, for example in analog video channel multiplexing for picture-in-picture displays or infrared imaging sensors. In such applications, different analog signals are individually selected for output.
Several arrangements have been proposed to select individual signals for output. Typical switching arrangements employ individual switches within the signal paths of each input signal.
Referring to FIG. 1A, for example, a conventional switching arrangement may include multiple input signals INPUTS A-D, respective switches SA-SD, and a buffering feedthrough operational amplifier (op-amp) BOA. Complementary Metal Oxide Semiconductor Field Effect Transistors (CMOSFETs) may be used to implement the switches SA-SD. The switches SA-SD are individually enabled by enable signals EN1, EN1*, EN2, EN2*, EN3, EN3* and EN4, EN4* generated by, for example, a Timing Generator with various logic components. The input signals INPUTS A-D are individually selected by the switches SA-SD. When closed, the switches provide current paths for the input signals INPUTS A-D to be conducted and charge the stray capacitance at the input of the op-amp, BOA. The input signal selected by the switches is fed through the op-amp BOA and output as an output voltage, V.sub.OUT.
FIGS. 1B and 1C illustrate in detail the configuration of a typical CMOS switch employed in a signal path. In the illustrated example, the configuration of the CMOS switch SA depicted in FIG. 1A is shown in detail. Referring to FIG. 1B, the CMOS switch SA comprises parallel-connected complementary MOSFETs. Enable signals EN1 and EN1* are input at the gates of the MOSFETs to activate the switch SA and select the corresponding input signal INPUT A. Referring to FIG. 1C, the two MOSFETs are N and P channel MOS transistors, with parasitic capacitances CGD and CGS across the gates of the MOSFETs. The two complementary MOSFETs form a switch that is essentially an open circuit from one end to the other when the N channel's gate is a logic low and the P channel's gate is a logic high. To turn the switch SA on, the enable signal EN1 is applied at a high logic level to the N channel and the enable signal EN1* is applied at a low logic level at the P channel.
The variable resistances RP and RN represent the finite resistances of each MOSFET when it is turned on, somewhere in the 1 K.OMEGA. to 10 K.OMEGA. range, depending on the geometry of the MOSFET and the process parameters which determine the resistance range. The resistances of the MOSFETs are non-linear because they are a function of the magnitude of the current which passes through them, which depends on the charge on the capacitance and the voltage across the capacitances CGD and CGS. These non-linear resistances cause distortions in the selected signal.
FIG. 2 depicts a timing diagram illustrating the operation of the conventional switching arrangement depicted in FIG. 1A. Referring to FIG. 2, when the enable signal EN1 is high and EN1* is low, V.sub.OUT corresponds to INPUT A. When the enable signal EN2 is high and EN2* is low, V.sub.OUT corresponds to INPUT B. When the enable signal EN3 is high and EN3* is low, V.sub.OUT corresponds to INPUT C. Finally, when the enable signal EN4 is high and EN4* is low, V.sub.OUT corresponds to INPUT D. This operation is also shown in Table I below.
TABLE I EN1 EN1* EN2 EN2* EN3 EN3* EN4 EN4* Vout 1 0 0 1 0 1 0 1 INPUT A 0 1 1 0 0 1 0 1 INPUT B 0 1 0 1 1 0 0 1 INPUT C 0 1 0 1 0 1 1 0 INPUT D
Conventional switching arrangements such as that depicted in FIG. 1A employ separate switches for each of the input signals INPUTS A-D. A problem with such arrangements is that capacitive coupling may occur between the input enable signals EN1-EN4* and the input signals INPUTS A-D through the stray capacitances CGD and CGS. This capacitive coupling creates non-linearities which may cause significant distortion in the output signal. Also, a non-linear resistance appears across each switch, creating a source of additional non-linearities which further distort the output signal.
In an effort to reduce these negative effects, another switching arrangement has been proposed, in which input signals are input into differential transistor amplifiers, and the differential amplifiers are individually selected using a current steering long tail switch. The current steering long tail switch steers the current from a long tail current source, which ideally operates electrically like a long rope or tail to pull down on the common sources of a differential amplifier, causing that differential amplifier to produce a signal corresponding to the input signal. The differential amplifiers and the current steering long tail switch are arranged within an operational amplifier loop, and signal selection is performed within the op-amp. Non-linearities caused by capacitive coupling and non-linear resistance are attenuated by an amount equal to the open loop gain of the op-amp. However, this arrangement is typically implemented with bipolar transistors, requiring a complex configuration of blocking diodes, switches and resistors for optimum performance. Furthermore, the current steering long tail switch is typically implemented with a single bipolar transistor, which has a high transconductance but causes capacitive coupling due to the edge coupling from the base of the transistor to the collector of the transistor, resulting in a distorted output signal from charge coupling back to the input.
Thus, there is a need for a multiple input channel selection system that eliminates the distortion in an output signal caused by switching without requiring complex circuitry.